(1) Field of the Invention
The present invention relates to a technique for conducting a test on a semiconductor memory mounted together with a logic section on a single chip to configure a semiconductor device.
(2) Description of the Related Art
In response to demands for more density and more integration of a semiconductor device, recently, there is developed as such semiconductor device a system LSI having a configuration that a plurality of functional blocks are integrated on a single chip. Further, there is also developed a merged DRAM (Dynamic Random Access Memory)/logic LSI having a configuration that a semiconductor memory such as a large capacity memory (e.g., a DRAM) is mounted together with a logic section on a single chip. Such merged DRAM/logic LSI realizes data access with a multi-bit bus width and achieves improved performance by making use of its characteristics.
In a case where a memory block such as a DRAM is singly subjected to a test, however, a merged DRAM/logic LSI has the following disadvantage. That is, since terminals for directly exchanging data with the memory block with a multi-bit bus width are small in number, such test is conducted by input/output of data of several bits.
Hereinafter, description will be given of a conventional semiconductor memory (refer to, e.g., JP06-290587A) with reference to the drawings.
FIG. 8 is a block diagram illustrating a semiconductor device including the conventional semiconductor memory. As illustrated in FIG. 8, the semiconductor device 1 includes a logic section 2 and the semiconductor memory 3. The semiconductor memory 3 includes a memory core 4, a control circuit 5 controlling the memory core 4, and a data input/output circuit 6. Herein, the data input/output circuit 6 exchanges internal data with the memory core 4. In a normal operation, the data input/output circuit 6 exchanges data with the logic section 2. In a test, the data input/output circuit 6 receives test data from a test data input terminal and outputs test data to a test data output terminal.
With reference to FIGS. 9 and 10, next, description will be given of data write sequences and data read sequences in a test conducted on the semiconductor memory 3 of the semiconductor device 1.
FIG. 9 illustrates the data write sequences in the test. As illustrated in FIG. 9, a data bit width (e.g., four bits in FIG. 9) in the test is restricted in a memory cell array including a plurality of memory cell blocks. Herein, data is written with the data bit width (four bits). In order to write data to one memory cell block, for example, it is necessary to perform “n” data write operations (a first data write operation, a second data write operation, a third data write operation, . . . and an “n”-th data write operation).
FIG. 10 illustrates the data read sequences in the test. As illustrated in FIG. 10, data is read with the data bit width as in the aforementioned data write operation. Therefore, in order to read data from one memory cell block, it is necessary to perform “n” data read operations (a first data read operation, a second data read operation, a third data read operation, and an “n”-th data read operation).
In the conventional semiconductor device, for example, a merged LSI having a configuration that a semiconductor memory such as a large capacity memory (e.g., a DRAM) is mounted together with a logic section on a single chip, when a test is conducted on the semiconductor memory, terminals for performing data input/output with a data bit width for data exchange with the logic section in the normal operation cannot be secured in number. Consequently, the test must be conducted with a data bus width in a range from several bits to several tens of bits, so that there arises a problem that much time and cost are expended for such test.